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KAD5512HP preliminary 300 unicorn park dr., woburn, ma 01801 sales: 1-781-497-0060 sales@kenetinc.com femtocharge is a registered trademark of kenet, inc. copyright ? 2008, kenet, inc. rev 0.5 page 1 general description the KAD5512HP is the high-performance member of the kad5512 family of 12-bit analog-to-digital converters. designed with kenet?s proprietary femtocharge ? technology on a standard cmos process, the family supports sampling rates of up to 250msps. the KAD5512HP is part of a pin-compatible portfolio of 10, 12 and 14-bit a/ds with sample rates ranging from 125msps to 500msps. a serial peripheral interface (spi) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset. digital output data is presented in selectable lvds or cmos formats. the KAD5512HP is available in 72- and 48-contact qfn packages with an exposed paddle. operating from a 1.8v supply, performance is specified over the full industrial temperature range (-40 to +85c). features ? pin-compatible with the kad5512p family, offering 2.5db higher snr ? programmable gain and offset control ? 950mhz analog input bandwidth ? 52fs clock jitter ? over-range indicator ? selectable clock divider: 1, 2 or 4 ? clock phase selection ? nap and sleep modes ? two?s complement, gray code or binary data format ? sdr/ddr lvds-compatible or lvcmos outputs ? programmable built-in test patterns ? 1.8v analog and digital supplies applications ? power amplifier linearization ? radar and satellite antenna array processing ? broadband communications ? high-performance data acquisition ? communications test equipment ? wimax and microwave receivers high performance 12-bit, 250/210/170/125msps adc key specifications ? snr = 67.2dbfs for f in = 124mhz (-1dbfs) ? sfdr = 81dbc for f in = 124mhz (-1dbfs) ? power consumption ? 400/313mw @ 250/125msps (sdr mode) ? 347/269mw @ 250/125msps (ddr mode) pin-compatible family model resolution speed (msps) kad5514p-25 14 250 kad5514p-21 14 210 kad5514p-17 14 170 kad5512p-25, KAD5512HP-25 12 250 kad5512p-21, KAD5512HP-21 12 210 kad5512p-17, KAD5512HP-17 12 170 kad5512p-50 12 500 kad5514p-12 14 125 kad5512p-12, KAD5512HP-12 12 125 kad5510p-50 10 500
KAD5512HP rev 0.5 preliminary page 2 table of contents section pages section pages electrical specifications 3?7 serial peripheral interface 20?26 dc specifications 3 spi physical interface 21 ac specifications 4 spi configuration 22 digital specifications 5 dut information 23 switching specifications 6 dut configuration/control 23 timing diagrams 6 dut test 25 absolute maximum ratings 7 spi memory map 26 thermal impedance 7 equivalent circuits 27 esd 7 layout considerations 27 pinout/package information 8?11 definitions 28 pin descriptions?72qfn 8 outline dimensions?72qfn 29 pin configuration?72qfn 9 outline dimensions?72qfn 30 pin descriptions?48qfn 10 ordering guide 31 pin configuration?48qfn 11 revision history 31 typical performance characteristics 12?15 theory of operation 16?19 functional description 16 power-on calibration 16 user-initiated reset 17 analog input 17 clock input 18 jitter 18 voltage reference 18 digital outputs 18 power dissipation 19 nap/sleep 19 data format 19
KAD5512HP rev 0.5 preliminary page 3 electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40 c to +85 c, a in = -1dbfs, f sample = maximum conversion rate (per speed grade). dc specifications KAD5512HP-25 KAD5512HP-21 KAD5512HP-17 KAD5512HP-12 parameter symbol conditions min typ max min typ max min typ max min typ max units analog input full-scale analog input range v fs differential 1.38 1.45 1.59 1.38 1.45 1.59 1.38 1.45 1.59 1.38 1.45 1.59 v pp input resistance r in differential 1000 1000 1000 1000 ? input capacitance c in differential 4 4 4 4 pf full scale range temp. drift a vtc full temp 90 90 90 90 ppm/c input offset voltage v os 1.5 1.5 1.5 1.5 mv common-mode output voltage v cm 0.535 0.535 0.535 0.535 v power requirements 1.8v analog supply voltage avdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 1.8v analog supply current i avdd 154 tbd 142 tbd 130 tbd 116 tbd ma 1.8v digital supply current (sdr) i ovdd 68.0 tbd 64.6 tbd 61.7 tbd 58.1 tbd ma 1.8v digital supply current (ddr) i ovdd 38.9 tbd 36.9 tbd 35.3 tbd 33.2 tbd ma power supply rejection ratio psrr 0.5 0.5 0.5 0.5 mv/v power dissipation normal mode (sdr) p d 400 tbd 372 tbd 345 tbd 313 tbd mw normal mode (ddr) p d 347 tbd 322 tbd 298 tbd 269 tbd mw nap mode p d 40 tbd 40 tbd 40 tbd 40 tbd mw sleep mode p d 10 tbd 10 tbd 10 tbd 10 tbd mw gain error e g 0.6 0.6 0.6 0.6 %
KAD5512HP rev 0.5 preliminary page 4 ac specifications KAD5512HP-25 KAD5512HP-21 KAD5512HP-17 KAD5512HP-12 parameter symbol conditions min typ max min typ max min typ max min typ max units differential nonlinearity dnl f in = 10mhz tbd tbd tbd tbd tbd tbd tbd tbd lsb integral nonlinearity inl f in = 10mhz tbd tbd tbd tbd tbd tbd tbd tbd lsb signal-to-noise ratio snr f in = 10mhz 67.5 68.0 68.4 68.7 dbfs f in = 70mhz 67.4 67.8 68.3 68.6 dbfs f in = 140mhz tbd 67.2 tbd 67.6 tbd 68.0 tbd 68.2 dbfs f in = 230mhz 66.9 67.6 68.0 68.0 dbfs f in = 400mhz 65.9 tbd tbd tbd dbfs f in = 974mhz 62.2 tbd tbd tbd dbfs signal-to-noise and distortion sinad f in = 10mhz 66.2 66.7 67.0 67.3 dbfs f in = 70mhz 66.1 66.5 67.0 67.3 dbfs f in = 140mhz tbd 65.6 tbd 66.0 tbd 66.4 tbd 66.6 dbfs f in = 230mhz 65.4 66.9 67.3 67.3 dbfs f in = 400mhz 63.4 tbd tbd tbd dbfs f in = 974mhz 54.0 tbd tbd tbd dbfs spurious-free dynamic range sfdr f in = 10mhz 85 84 85 84 dbc f in = 70mhz 84 83 82 82 dbc f in = 140mhz tbd 83 tbd 80 tbd 78 tbd 77 dbc f in = 230mhz 77 77 76 76 dbc f in = 400mhz 71 tbd tbd tbd dbc f in = 974mhz 57 tbd tbd tbd dbc two-tone sfdr 2tsfdr f in = 10mhz tbd tbd tbd tbd dbc f in = 124mhz tbd tbd tbd tbd tbd tbd tbd tbd dbc f in = 170mhz tbd tbd tbd tbd dbc word error rate 10 -12 10 -12 10 -12 10 -12 full power bandwidth fpbw 950 950 950 950 mhz effective number of bits enob f in = 10mhz 10.7 10.8 10.8 10.9 bits f in = 70mhz 10.7 10.8 10.8 10.9 bits f in = 140mhz tbd 10.6 tbd 10.7 tbd 10.7 tbd 10.8 bits f in = 230mhz 10.6 10.8 10.9 10.9 bits f in = 400mhz 10.2 tbd tbd tbd bits f in = 974mhz 8.7 tbd tbd tbd bits intermodulation distortion imd f in = 10mhz tbd tbd tbd tbd dbfs f in = 70mhz -91.5 tbd tbd tbd tbd tbd tbd tbd dbfs f in = 170mhz -86.5 tbd tbd tbd dbfs minimum conversion rate f s min tbd tbd tbd tbd msps maximum conversion rate f s max 250 210 170 125 msps
KAD5512HP rev 0.5 preliminary page 5 digital specifications parameter symbol conditions min typ max units inputs input current high (resetn) i ih vin = 1.8v 0 1 10 a input current low (resetn) i il vin = 0v 25 50 75 a input current high (outmode, nap/slp, clkdiv, outfmt ) i ih tbd 25 tbd a input current low (outmode, nap/slp, clkdiv, outfmt ) i il tbd 25 tbd a input capacitance c di 3 pf lvds outputs differential output voltage v t 210 mv output rise time t r 500 ps output fall time t f 500 ps cmos outputs voltage output high v oh ovdd-0.1 v voltage output low v ol 0.1 v output offset voltage v os tbd mv output rise time t r tbd ns output fall time t f tbd ns
KAD5512HP rev 0.5 preliminary page 6 switching specifications timing diagrams parameter symbol min typ max units adc aperture delay t a 375 ps rms aperture jitter j a 52 fs input clock to output clock propagation delay t cpd tbd tbd tbd ps input clock to data propagation delay t pd tbd tbd tbd ps output clock to data propagation delay t dc tbd tbd tbd ps latency (pipeline delay) l 7.5 cycles over voltage recovery t ovr 1 cycles figure 1a. lvds timing diagram?ddr figure 2a. cmos timing diagram?ddr figure 1b. lvds timing diagram?sdr figure 2b. cmos timing diagram?sdr inp inn clkp clkn clkoutp clkoutn d[10/8/6/4/2/0]n d[10/8/6/4/2/0]p t a t cpd t dc t pd odd bits n-l even bits n-l odd bits n-l+1 even bits n-l+1 latency = l cycles sample n odd bits n-l+2 even bits n-l+2 odd bits n inp inn clkp clkn clkout d[10/8/6/4/2/0] t a t cpd t dc t pd odd bits n-l even bits n-l odd bits n-l+1 even bits n-l+1 latency = l cycles sample n odd bits n-l+2 even bits n-l+2 odd bits n inp inn clkp clkn clkoutp clkoutn d[11:0]n d[11:0]p t a t cpd t dc t pd data n-l latency = l cycles sample n data n-l+1 data n-l+2 data n inp inn clkp clkn clkout t a t cpd t dc t pd latency = l cycles sample n d[11:0] data n-l data n-l+1 data n-l+2 data n
KAD5512HP rev 0.5 preliminary page 7 absolute maximum ratings 1 1. exposing the device to levels in excess of the ma ximum ratings may cause permanent damage. exposure to maximum conditions for extended periods may affect device reliability. thermal impedance 2. paddle soldered to ground plane. esd electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, ba lls, exposed paddle, etc.) of an integrated circuit. industry-standard protection techniques have been utilized in the design of this prod- uct. however, reasonable care must be taken in the storage and handling of esd sensitive products. contact kenet for the specific esd sensitivity rating of this product. parameter min max unit avdd to avss -0.4 2.1 v ovdd to ovss -0.4 2.1 v analog inputs to avss -0.4 avdd + 0.3 v clock inputs to avss -0.4 avdd + 0.3 v logic input to avss -0.4 ovdd + 0.3 v logic inputs to ovss -0.4 ovdd + 0.3 v operating temperature -40 85 c storage temperature -65 150 c junction temperature 150 c avss to ovss -0.3 0.3 v parameter symbol typ unit junction to paddle 2 jp 30 c/w junction to case 2 jc tbd c/w junction to ambient 2 ja tbd c/w
KAD5512HP rev 0.5 preliminary page 8 pin descriptions?72qfn lvcmos output mode functionality is shown in brackets (nc = no connection) pin # lvds [lvcmos] name lvds [lvcmos] function 1, 6, 19, 24, 71 avdd 1.8v analog supply 2-5, 13, 14, 17, 18, 28-31 dnc do not connect 7, 8, 11, 12, 72 avss analog ground 9, 10 vinn, vinp analog input negative, positive 15 vcm common mode output 16 clkdiv clock divider control 20, 21 clkp, clkn clock input true, complement 22 outmode output mode (lvds, lvcmos) 23 napslp power control (nap, sleep modes) 25 resetn power on reset (active low) 26, 45, 55, 65 ovss output ground 27, 36, 56 ovdd 1.8v output supply 32, 33 d0n, d0p [nc, d0] lvds bit 0 (lsb) output complement, true [nc, lvcmos bit 0] 34, 35 d1n, d1p [nc, d1] lvds bit 1 output complement, true [nc, lvcmos bit 1] 37, 38 d2n, d2p [nc, d2] lvds bit 2 output complement, true [nc, lvcmos bit 2] 39, 40 d3n, d3p [nc, d3] lvds bit 3 output complement, true [nc, lvcmos bit 3] 41, 42 d4n, d4p [nc, d4] lvds bit 4 output complement, true [nc, lvcmos bit 4] 43, 44 d5n, d5p [nc, d5] lvds bit 5 output complement, true [nc, lvcmos bit 5] 46 rlvds lvds bias resistor (connect to ovss with a 10k ? , 1% resistor) 47, 48 clkoutn, clkoutp [nc, clkout] lvds clock output complement, true [nc, lvcmos clkout] 49, 50 d6n, d6p [nc, d6] lvds bit 6 output complement, true [nc, lvcmos bit 6] 51, 52 d7n, d7p [nc, d7] lvds bit 7 output complement, true [nc, lvcmos bit 7] 53, 54 d8n, d8p [nc, d8] lvds bit 8 output complement, true [nc, lvcmos bit 8] 57, 58 d9n, d9p [nc, d9] lvds bit 9 output complement, true [nc, lvcmos bit 9] 59, 60 d10n, d10p [nc, d10] lvds bit 10 output complement, true [nc, lvcmos bit 10] 61, 62 d11n, d11p [nc, d11] lvds bit 11(msb) output complement, true [nc, lvcmos bit 11] 63, 64 orn, orp [nc, or] lvds over range complement, true [nc, lvcmos over range] 67 csb spi chip select (active low) 68 sclk spi clock 69 sdio spi serial data input/output 70 outfmt output data format (two?s comp., gray code, offset binary) exposed paddle avss analog ground 66 sdo spi serial data output (4.7k ? pull-up to ovdd is required)
KAD5512HP rev 0.5 preliminary page 9 pin configuration?72qfn figure 3. 72 qfn pin configuration kad5512 top view not to scale avdd dnc dnc dnc dnc avdd avss avss vinn vinp avss avdd dnc dnc vcm clkdiv dnc dnc d6p d6n clkoutp clkoutn rlvds ovss d5p d5n d4p d4n d3p d3n d2p d2n d8p d8n d7p d7n 72 qfn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 50 49 48 47 46 45 44 43 42 41 40 39 38 37 54 53 52 51
KAD5512HP rev 0.5 preliminary page 10 pin descriptions?48qfn lvcmos output mode functionality is shown in brackets (nc = no connection) pin # lvds [lvcmos] name lvds [lvcmos] function 1, 9, 13, 17, 47 avdd 1.8v analog supply 2-4, 11, 21, 22 dnc do not connect 5, 8, 12, 48 avss analog ground 6, 7 vinn, vinp analog input negative, positive 10 vcm common mode output 14, 15 clkp, clkn clock input true, complement 16 napslp power control (nap, sleep modes) 18 resetn power on reset (active low) 19, 29, 41 ovss output ground 20, 42 ovdd 1.8v output supply 23, 24 d0n, d0p [nc, d0] lvds bit 0 (lsb) output complement, true [nc, lvcmos bit 0] 25, 26 d1n, d1p [nc, d1] lvds bit 1 output complement, true [nc, lvcmos bit 1] 27, 28 d2n, d2p [nc, d2] lvds bit 2 output complement, true [nc, lvcmos bit 2] 30 rlvds lvds bias resistor (connect to ovss with a 10k ? , 1% resistor) 31, 32 clkoutn, clkoutp [nc, clkout] lvds clock output complement, true [nc, lvcmos clkout] 33, 34 d3n, d3p [nc, d3] lvds bit 3 output complement, true [nc, lvcmos bit 3] 35, 36 d4n, d4p [nc, d4] lvds bit 4 output complement, true [nc, lvcmos bit 4] 37, 38 d5n, d5p [nc, d5] lvds bit 5 output complement, true [nc, lvcmos bit 5] 39, 40 orn, orp [nc, or] lvds over range complement, true [nc, lvcmos over range] 43 sdo spi serial data output (4.7k ? pull-up to ovdd is required) 44 csb spi chip select (active low) 45 sclk spi clock 46 sdio spi serial data input/output exposed paddle avss analog ground
KAD5512HP rev 0.5 preliminary page 11 pin configuration?48qfn figure 4. 48qfn pin configuration avdd dnc dnc dnc avdd avss avss vinn vinp avss dnc vcm avdd clkp clkn napslp avdd resetn ovss ovdd dnc dnc d0n d0p clkoutp clkoutn rlvds ovss d4p d4n d3p d3n d2p d2n avss avdd sdio sclk csb sdo ovss orp orn kad5512 top view not to scale 48 qfn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 d1p d1n d5p d5n ovdd
KAD5512HP rev 0.5 preliminary page 12 typical performance curves figure 5. snr & sfdr vs. f in figure 6. hd2 & hd3 vs. f in figure 7. snr & sfdr vs. a in figure 8. hd2 & hd3 vs. a in figure 9. snr & sfdr vs. f sample figure 10. hd2 & hd3 vs. f sample tbd tbd tbd 50 55 60 65 70 75 80 85 90 0 200 400 600 800 1000 input frequency (mhz) snrfs (dbfs) & sfdr (dbc) snrfs sfdr tbd 60 65 70 75 80 85 90 30 80 130 180 230 sample rate (msps) snrfs (dbfs) & sfdr (dbc) snrfs sfdr
KAD5512HP rev 0.5 preliminary page 13 typical performance curves figure 11. power vs. f sample (lvds mode) figure 12. differential nonlinearity figure 13. integral nonlinearity figure 14. snr & sfdr vs. vcm figure 15. noise histogram figure 16. single tone spectrum @ 10 mhz tbd tbd tbd tbd tbd 200 250 300 350 400 450 30 80 130 180 230 sample rate (msps) total power (mw)
KAD5512HP rev 0.5 preliminary page 14 typical performance curves figure 17. single tone spectrum @ 70 mhz figure 18. single tone spectrum @ 140 mhz figure 19. single tone spectrum @ 240 mhz figure 20. single tone spectrum @ 500 mhz figure 21. two-tone spectrum @ 10 mhz figure 22. two-tone spectrum @ 70 mhz tbd tbd tbd tbd tbd tbd
KAD5512HP rev 0.5 preliminary page 15 typical performance curves figure 23. two-tone spectrum @ 140 mhz figure 24. two-tone spectrum @ 240 mhz figure 25. two-tone spectrum @ 500 mhz figure 26. snr & sfdr vs. temperature figure 27. snr & sfdr vs. power supply voltage 60 65 70 75 80 85 90 -40-20 0 20406080 temperature (c) snrfs (dbfs) & sfdr (dbc) snrfs sfdr tbd tbd tbd 60 65 70 75 80 85 90 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 avdd & ovdd (v) snrfs (dbfs) & sfdr (dbc) snrfs sfdr
KAD5512HP rev 0.5 preliminary page 16 functional description the KAD5512HP is based upon a 12-bit, 250msps a/d converter core that utilizes a pipelined successive approximation architecture (figure 28). the input voltage is captured by a sample-hold amplifier (sha) and converted to a unit of charge. proprietary charge domain techniques are used to successively compare the input to a series of reference charges. decisions made during the successive approximation operations determine the digital code for each input value. the converter pipeline requires six samples to produce a result. digital e rror correction is also ap- plied, resulting in a total latency of seven and a half clock cycles. this is evident to the user as a time lag between the start of a conversion and the data be- ing available on the digital outputs. the KAD5512HP family offers 2.5db improvement in snr over the kad5512p by simultaneously sampling the input signal with two adc cores in parallel and summing the digital result. since the input signal is correlated between the two cores and noise is not, an increase in snr is achiev ed. as a result of this ar- chitecture, indexed spi operations must be executed on each core in series. refer to the indexed dut con- figuration/control section for more details. power-on calibration at start-up, the core performs a self-calibration to minimize gain and offset e rrors. an internal power-on- reset (por) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. the following conditions must be adhered to for the power-on calibration to execute successfully: ? a frequency-stable conversion clock must be applied to the clkp/clkn pins ? dnc pins (especially 3, 4 and 18) must not be pulled up or down ? sdo (pin 66) must be high ? resetn (pin 25) must begin low ? spi communications must not be attempted a user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. the sdo pin requires an external 4.7k ? pull-up to ovdd. if the sdo pin is pulled low externally during power-up, calibration will not be executed properly. after the power supply has stabilized the internal por releases resetn and an internal pull-up pulls it high, which starts the calibration sequence. the resetn pin should be connected to an open-drain driver with a drive strength of less than 0.5ma. figure 28. adc core block diagram
KAD5512HP rev 0.5 preliminary page 17 the calibration sequence is initiated on the rising edge of resetn, as shown in figure 29. the over- range output (or) is set hi gh once resetn is pulled low, and remains in that state until calibration is com- plete. the or output returns to normal operation at that time, so it?s important that the analog input be within the converter?s full-scale range in order to ob- serve the transition. if the input is in an over-range condition the or pin will st ay high and it will not be possible to detect the end of the calibration cycle. while resetn is low, the output clock (clkoutp/clkoutn) stops toggling and is set low. normal operation of the output clock resumes at the next input clock edge (clkp/clkn) after resetn is deasserted. at 250msps the nominal calibration time is tbdms. figure 29. calibration timing user initiated reset recalibration of the adc can be initiated at any time by driving the resetn pin low for a minimum of one clock cycle. an open-drain driver with a drive strength of less than 0.5ma is recommended. as is the case during power-on reset, the sdo, resetn and dnc pins must be in the proper state for the calibra- tion to successfully execute. analog input the adc core contains a fully differential input (vinp/vinn) to the sample and hold amplifier (sha). the ideal full-scale input voltage is 1.45v, centered at the vcm voltage of 0.535v as shown in figure 30. figure 30. analog input range best performance is obtained when the analog in- puts are driven differentially. the common mode out- put voltage, vcm, should be used to properly bias the inputs as shown in figures 31 through 33. an rf transformer will give the best noise and distortion per- formance for wideband and/or high intermediate frequency (if) inputs. two different transformer input schemes are shown in figures 31 and 32. figure 31. transformer input for general purpose applications figure 32. transmission-line transformer input for high if applications a back-to-back transformer scheme is used to im- prove common mode rejection, which keeps the common mode level of the input matched to vcm. the value of the shunt resistor should be determined based on the desired load impedance. the differen- tial input resistance of the KAD5512HP is 1000 ? . the sha design uses a switched capacitor input stage, which creates charge kick-back when the sampling capacitance is reconnected to the input voltage. this kick-back creates a disturbance at the input which must settle before the next sampling point. lower source impedance will result in faster
KAD5512HP rev 0.5 preliminary page 18 settling and improved performance. therefore a 1:1 transformer and low shunt resistance are recom- mended for optimal performance. figure 33. differential amplifier input a differential amplifier, as shown in figure 33, can be used in applications that re quire dc-coupling. in this configuration the amplifier will typically dominate the achievable snr and distortion performance. clock input the clock input circuit is a differential pair (see figure 36). driving these inputs with a high level (up to 1.8v pp on each input) sine or square wave will provide the lowest jitter performance. a transformer with 4:1 im- pedance ratio will provide increased drive levels. the recommended drive circui t is shown in figure 34. the clock can be driven single-ended, but this will reduce the edge rate an d may impact snr perform- ance. the clock inputs are internally self-biased to avdd/2 to facilitate ac coupling. figure 34. recommended clock drive a selectable 2x/4x divider is provided in series with the clock input. the divider can be used in the 2x mode with a sample clock equal to twice the desired sample rate. this will result in a clock input with 50% duty cycle and will maximi ze the converter?s perform- ance. table 1. clkdiv pin settings the clock divider can also be controlled through the spi port, which overrides the clkdiv pin setting. de- tails on this are contained in the serial peripheral in- terface section. a delay-locked loop (dll) generates internal clock signals for various stages with in the charge pipeline. if the frequency of the input clock changes, the dll may take up to 52 s to regain lock at 250msps. the lock time is inversely propor tional to the sample rate. jitter in a sampled data system, clock jitter directly im- pacts the achievable snr performance. the theoreti- cal relationship between clock jitter (t j ) and snr is shown in equation 1 and is illustrated in figure 35. equation 1. figure 35. snr vs. clock jitter this relationship shows the snr that would be achieved if clock jitter were the only non-ideal fac- tor. in reality, achievable snr is limited by internal factors such as linearity, aperture jitter and thermal noise. internal aperture jitter is the uncertainty in the sampling instant shown in fi gure 1. the internal aper- ture jitter combines with the input clock jitter in a root- sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. the total jitter, combined with other noise sources, then determines the achievable snr. voltage reference a temperature compensated voltage reference pro- vides the reference charges used in the successive approximation operations. the full-scale range of clkdiv pin divide ratio avss 2 float 1 avdd 4 ? ? ? ? ? ? ? ? = j in t f snr 2 1 log 20 10 tj=100ps tj=10ps tj=1ps tj=0.1ps 10 bits 12 bits 14 bits 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 input frequency - mhz snr - db
KAD5512HP rev 0.5 preliminary page 19 each a/d is proportional to the reference voltage. the voltage reference is internally bypassed and is not accessible to the user. digital outputs output data is available as a parallel bus in lvds- compatible or cmos modes. additionally, the data can be presented in either double data rate (ddr) or single data rate (sdr) formats. the even numbered output bits are active in ddr mode. when clkout is low the msb and all odd bits are output, while on the high phase the lsb and all even bits are presented. figures 1 and 2 show the timing relationships for lvds/cmos and ddr/sdr modes. the 48-qfn package option contains six lvds data outputs, and therefore can only support ddr mode. additionally, the drive current for lvds mode can be set to a nominal 3 ma or a power-saving 2 ma. the lower current setting can be used in designs where the receiver is in close physical proximity to the adc. the applicability of this setting is dependent upon the pcb layout, therefore the user should experiment to determine if performance degradation is observed. the output mode and lvds drive current are se- lected via the outmode pin as shown in table 3. table 2. outmode pin settings the output mode can also be controlled through the spi port, which overrides the outmode pin setting. details on this are contained in the serial peripheral interface section. an external resistor creates the bias for the lvds driv- ers. a 10k ? , 1% resistor must be connected from the rlvds pin to ovss. power dissipation the power dissipated by the KAD5512HP is primarily dependent on the sample rate, but is also related to the input signal in cmos output mode. there is a static bias in the analog supply, while the remaining power dissipation is linear ly related to the sample rate. the output supply dissipation changes to a lesser degree in lvds mode, but is more strongly re- lated to the clock frequency in cmos mode. figures 36 and 37 illustrate these relationships. figure 36. power vs. sample rate, lvds mode figure 37. power vs. sample rate, cmos mode nap/sleep portions of the device may be shut down to save power during times when operation of the adc is not required. two power saving modes are available: nap, and sleep. nap mode reduces power dissipa- tion to 40mw and recovers to normal operation in approximately 1 s. sleep mode reduces power dissi- pation to 10mw but requires 1ms to recover. the clock should remain running and at a fixed fre- quency during nap or sleep. recovery time from nap mode will increase if the clock is stopped, since the internal dll can take up to 52 s to regain lock at 250msps. by default after the device is powered on, the opera- tional state is controlled by the napslp pin as shown in table 4. outmode pin mode avss lvcmos float lvds, 3 ma avdd lvds, 2 ma tbd tbd
KAD5512HP rev 0.5 preliminary page 20 table 3. napslp pin settings the power down mode can also be controlled through the spi port, which overrides the napslp pin setting. details on this are contained in the serial pe- ripheral interface section. this is an indexed function when controlled from the spi, but a global function when driven from the pin. data format output data can be presented in three formats: two?s complement, gray code and offset binary. the data format is selected vi a the outfmt pin as shown in table 5. table 4. outfmt pin settings the data format can also be controlled through the spi port, which overrides the outfmt pin setting. de- tails on this are contained in the serial peripheral in- terface section. offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most posi- tive input to 0xfff (all ones). two?s complement cod- ing simply complements the msb of the offset binary representation. when calculating gray code the msb is unchanged. the remaining bits are computed as the xor of the current bit position and the next most significant bit. figure 38 shows this operation. figure 38. binary to gray code conversion converting back to offset binary from gray code must be done recursively, using the result of each bit for the next lower bit as shown in figure 39. figure 39. gray code to binary conversion mapping of the input voltage to the various data for- mats is shown in table 6. table 5. input voltage to output code mapping serial peripheral interface a serial peripheral interface (spi) bus is used to facili- tate configuration of the device and to optimize per- formance. the spi bus consists of chip select (csb), serial clock (sclk) and se rial data input/output (sdio). the maximum sclk rate is equal to the adc sample rate (f sample ) divided by 16 for write opera- tions and f sample divided by 66 for reads. at f sample = 250mhz, maximum sclk is 15.63mhz for writing and napslp pin mode avss normal float sleep avdd nap outfmt pin mode avss offset binary float two?s complement avdd gray code input voltage gray code ?full scale 000000000000 ?full scale + 1lsb 000000000001 +full scale 100000000000 offset binary 000000000000 000000000001 111111111111 two?s complement 100000000000 100000000001 011111111111 mid?scale 100000000000 000000000000 110000000000 +full scale ? 1lsb 111111111110 011111111110 100000000001
KAD5512HP rev 0.5 preliminary page 21 3.79mhz for write operations. there is no minimum sclk rate. the following sections describe various registers that are used to configure the spi or adjust performance or functional parameters. ma ny registers in the avail- able address space (0x00 to 0xff) are not defined in this document. additionally, within a defined register there may be certain bits or bit combinations that are reserved. undefined registers and undefined val- ues within defined registers are reserved and should not be selected. setting any reserved register or value may produce indeterminate results. spi physical interface the spi port operates in a half or full duplex mas- ter/slave configuration, with the KAD5512HP function- ing as a slave. multiple slave devices can interface to a single master. the chip-select bar (csb) pin deter- mines when a slave device is being addressed. multi- ple slave devices can be written to concurrently, but only one slave device can be read from at a given time. if multiple slave devices are selected for read- ing at the same time, the results will be indetermi- nate. the serial clock pin (sclk) provides synchronization for the data transfer. by default, all data is presented on the serial data input/output (sdio) pin. the state of the sdio pin is set automatically in the communi- cation protocol (described below). a dedicated se- rial data output pin (sdo) can be activated by set- ting 0x00[7] high to allow operation in full duplex mode. the communication protocol begins with an instruc- tion/address phase. the first rising sclk edge follow- ing a high to low transition on csb determines the beginning of the two-byte instruction/address com- mand. data can be presented in msb-first order or lsb-first order. the default is msb-first, but this can be changed by setting 0x00[6] high. figures 40 and 41 show the appropriate bit ordering for the msb-first and lsb-first modes, respectively. in msb-first mode the address is incremented for multi-byte transfers, while in lsb-first mode it?s decremented. in the default mode the msb is r/w, which deter- mines if the data is to be read (active high) or writ- ten. the next two bits, w1 and w0, determine the number of data bytes to be read or written (see ta- ble 6). the lower 13 bits contain the first address for the data transfer. this relati onship is illustrated in fig- ure 42, and timing values are given in the switching specifications section. after the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the adc (based on the r/w bit status). the data transfer will continue as long as csb remains low and sclk is active. stalling of the csb pin is al- lowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. for transfers of four bytes or more, csb is al- lowed stall in the middle of the instruction/address bytes or before the first data byte. if csb transitions to a high state after that point the state machine will reset and terminate the data transfer. figure 40. msb-first addressing figure 41. lsb-first addressing
KAD5512HP rev 0.5 preliminary page 22 table 6. byte transfer selection figures 43 and 44 illustrate the timing relationships for 2-byte and n-byte transfers, respectively. the opera- tion for a 3-byte transfer can be inferred from these diagrams. spi configuration address 0x00: chip_port_config bit ordering and spi reset are controlled by this regis- ter. bit order can be selected as msb to lsb (msb first) or lsb to msb (lsb first) to accommodate various mi- crocontrollers. bit 7 sdo active bit 6 lsb first setting this bit high configures the spi to inter- pret serial data as arriving in lsb to msb order. bit 5 soft reset setting this bit high resets all spi registers to default values. bit 4 reserved this bit should always be set high. bits 3:0 these bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. [w1:w0] bytes transferred 00 1 01 2 10 3 11 4 or more figure 44. n-byte transfer figure 43. 2-byte transfer figure 42. instruction/address phase
KAD5512HP rev 0.5 preliminary page 23 address 0x02: burst_end if a series of sequential registers are to be set, burst mode can improve throughput by eliminating redun- dant addressing. in 3-wire spi mode the burst is ended by pulling the csb pi n high. if the device is operated in 2-wire mode the csb pin is not available. in that case, setting the burst_end address deter- mines the end of the transfer. during a write opera- tion, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. bits 7:0 burst end address this register value determines the ending ad- dress of the burst data. dut information address 0x08: chip_id address 0x09: chip_version the generic die identifier and a revision number, re- spectively, can be read from these two registers. indexed dut configuration/control address 0x10: device_index_a a common spi map, which can accommodate sin- gle-channel or multi-channel devices, is used for all kenet adc products. certain configuration com- mands (identified as indexed in the spi map) can be executed on a per-converter basis. this register de- termines which converter is being addressed for an indexed command. it is impo rtant to note that only a single converter can be addressed at a time. this register defaults to 00h, indicating that no adc is addressed. single-channel adcs must set bit 0 of this register high in order to execute any indexed com- mands. address 0x20: offset_coarse address 0x21: offset_fine the input offset of each adc core can be adjusted in fine and coarse steps. both adjustments are made via an 8-bit word as detailed in table 7. the data for- mat is twos complement. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incre- mented or decremented value back to the same register. table 7. offset adjustments address 0x22: gain_coarse address 0x23: gain_medium address 0x24: gain_fine gain of each adc core can be adjusted in coarse, medium and fine steps. coarse gain is a 4-bit adjust- ment while medium and fine are 8-bit. the data for- mat is twos complement for all three registers. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incre- mented or decremented value back to the same register. table 8. coarse gain adjustment table 9. medium and fine gain adjustments address 0x25: modes two distinct reduced power modes can be selected. by default, the tri-level napslp pin can select normal parameter 0x20[7:0] coarse offset 0x21[7:0] fine offset steps 256 256 ?full scale (0x80) -24.0mv -1.7mv +full scale (0x7f) +23.8mv +1.7mv nominal step size 187.5 v 13.3 v mid?scale (0x00) 0.0mv 0.0mv parameter 0x22[3:0] coarse gain steps 16 ?full scale (0x08) -11.2% mid?scale (0x00) 0.0% +full scale (0x07) +9.8% nominal step size 1.4% parameter 0x23[7:0] medium gain 0x24[7:0] fine gain steps 256 256 ?full scale (0x80) -10.56% -1.06% mid?scale (0x00) 0.0% 0.0% +full scale (0x7f) +10.48% +1.05% nominal step size 0.0825% 0.00825%
KAD5512HP rev 0.5 preliminary page 24 operation, nap or sleep modes (refer to nap/sleep section). this functionality can be overridden and controlled through the spi. this is an indexed function when controlled from the spi, but a global function when driven from the pin. this register is not changed by a soft reset. table 10. power down control global dut configuration/control address 0x70: skew_diff the value in the skew_diff register adjusts the timing skew between the two adcs cores. the nominal range and resolution of this adjustment are given in table 11. the default value of this register after power- up is 00h. table 11. differential skew adjustment address 0x71: phase_slip when using a clock divider, it?s not possible to deter- mine the synchronization of the incoming and divided clock phases. this is particularly important when multi- ple adcs are used in a time-interleaved system. the phase slip feature allows the rising edge of the divided clock to be advanced by one input clock cycle, as shown in figure 45. figure 45. phase slip address 0x72: clock_divide the KAD5512HP has a selectable clock divider that can be set to divide by four, two or one (no division). by default, the tri-level clkdiv pin selects the divisor (refer to clock input section). this functionality can be overridden and controlled through the spi, as shown in table 12. this register is not changed by a soft reset. table 12. clock divider selection address 0x73: output_mode_a the output_mode_a register controls the physical out- put format of the data, as well as the logical coding. the KAD5512HP can present output data in two physi- cal formats: lvds or lvcmos. additionally, the drive strength in lvds mode can be set high (3ma) or low (2ma). by default, the tri-level outmode pin selects the mode and drive level (refer to digital outputs sec- tion). this functionality can be overridden and con- trolled through the spi, as shown in table 13. data can be coded in three possible formats: two?s complement, gray code or offset binary. by default, the tri-level outfmt pin selects the data format (refer to data format section). this functionality can be over- ridden and controlled through the spi, as shown in ta- ble 14. this register is not changed by a soft reset. value 0x25[2:0] power down mode 000 pin control 001 normal operation 010 nap mode 100 sleep mode parameter 0x70[7:0] differential skew steps 256 ?full scale (0x08) -6.5ps mid?scale (0x00) 0.0ps +full scale (0x07) +6.5ps nominal step size 51fs value 0x72[2:0] clock divider 000 pin control 001 divide by 1 010 divide by 2 100 divide by 4
KAD5512HP rev 0.5 preliminary page 25 table 13. output mode control table 14. output format control address 0x74: output_mode_b address 0x75: config_status bit 6 dll range this bit sets the dll operating range to fast (tbd2msps to 250msps) or slow (40 to tbd1msps). bit 4 ddr enable setting this bit enables double data-rate mode. the output_mode_b and config_status registers are used in conjunction to enable ddr mode and select the frequency range of the dll clock generator. the method of setting these options is different from the other registers. figure 46. setting output_mode_b register the procedure for setting output_mode_b is shown in figure 46. read the conten ts of output_mode_b and config_status and xor them. then xor this result with the desired value for output_mode_b and write that xor result to the register. dut test the KAD5512HP can produce preset or user defined patterns on the digital outputs to facilitate in-situ test- ing. a static word can be placed on the output bus, or two different words can alternate. in the alternate mode, the values defined as word 1 and word 2 (as shown in table 13) are set on the output bus on alter- nating clock phases. address 0xc0: test_io bits 7:6 user test mode these bits set the test mode to static (0x00) or alternate (0x01) mode. other values are re- served. the four lsbs in this register (output test mode) deter- mine the test pattern in combination with registers 0xc2 through 0xc5. refer to table 15. table 15. output test modes address 0xc2: user_patt1_lsb address 0xc3: user_patt1_msb these registers define the lower and upper eight bits, respectively, of the first user-defined test word. address 0xc2: user_patt2_lsb address 0xc3: user_patt2_msb these registers define the lower and upper eight bits, respectively, of the second user-defined test word. value 0x93[7:5] output mode 000 pin control 001 lvds 2ma 010 lvds 3ma 100 lvcmos value 0x93[2:0] output format 000 pin control 001 two?s complement 010 gray code 100 offset binary value 0xc0[3:0] output test mode 0000 off 0001 midscale 0010 positive full-scale 0011 negative full-scale 0100 checkerboard 0101 reserved 0110 reserved 0111 one/zero 1000 user pattern word 1 0x8000 0xffff 0x0000 0xaaaa n/a n/a 0xffff user_patt1 word 2 n/a n/a n/a 0x5555 n/a n/a 0x0000 user_patt2
KAD5512HP rev 0.5 preliminary page 26 spi memory map table 16. spi memory map addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value ( hex ) indexed/ global 00 port_config sdo active lsb first soft reset mirror (bit5) mirror (bit6) mirror (bit7) 00h g 01 reserved 02 burst_end 00h g 03-07 reserved 08 chip_id read only g 09 chip_version read only g 10 device_index_a adc00 00h i 11-1f reserved 20 offset_coarse cal. value i 21 offset_fine cal. value i 22 gain_coarse cal. value i 23 gain_medium cal. value i 24 g ain_fine cal. value i 25 modes 00h not affected by soft reset i 26-5f reserved 60-6f reserved 70 reserved 71 phase_slip next clock edge 00h g 72 clock_divide 00h not affected by soft reset g 73 output_mode_a 00h not affected by soft reset g 74 output_mode_b dll range 0=fast 1=slow ddr enable 00h not affected by soft reset g 75 config_status xor result xor result read only g 76-bf reserved c1 reserved 00h g c2 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h g c3 user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 00h g c4 user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h g c5 user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 00h g c6-ff reserved reserved dut test spi config dut info indexed dut config/control global dut config/control g 00h burst end address [7:0] test_io user test mode [2:0] 00=single 01=alternate 10=single once 11=alternate once reset pn long gen chip id # chip version # reserved output mode [2:0] 000=pin control 001=lvds 2ma 010=lvds 3ma 100=lvcmos other codes=reserved coarse offset reserved medium gain c0 output test mode [3:0] 7=one/zero word toggle 8=user input 9-15=reserved 0=off 1=midscale short 2=+fs short 3= ? fs short 4=checker board 5=reserved 6=reserved reserved reserved reserved reset pn short gen reserved clock divide [2:0] 000=pin control 001=divide by 1 010=divide by 2 100=divide by 4 other codes=reserved reserved output format [2:0] 000=pin control 001=twos complement 010=gray code 100=offset binary other codes=reserved reserved reserved coarse gain reserved reserved power down mode [2:0] 000=pin control 001=normal operation 010=nap 100=sleep other codes=reserved fine gain fine offset
KAD5512HP rev 0.5 preliminary page 27 equivalent circuits figure 47. analog inputs figure 48. clock inputs figure 49. tri-level digital inputs figure 50. digital inputs figure 51. lvds outputs figure 52. cmos outputs figure 53. vcm_out output layout considerations split ground and power planes data converters operating at high sampling frequen- cies require extra care in pc board layout. many complex board designs benefit from isolating the analog and digital sections. analog supply and ground planes should be laid out under signal and clock inputs. locate the digital planes under outputs and logic pins. grounds should be joined under the chip. clock input considerations use matched transmission lines to the transformer in- puts for the analog input and clock signals. locate transformers and terminations as close to the chip as possible. avdd clkp clkn avdd avdd to charge pipeline 11k ? 11k ? avdd 18k ? 18k ?
KAD5512HP rev 0.5 preliminary page 28 exposed paddle the exposed paddle must be electrically connected to analog ground (avss) and should be connected to a large copper plane using numerous vias for opti- mal thermal performance. bypass and filtering bulk capacitors should have low equivalent series re- sistance. tantalum is a g ood choice. for best per- formance, keep ceramic bypass capacitors very close to device pins. longer traces will increase in- ductance, resulting in diminished dynamic perform- ance and accuracy. make sure that connections to ground are direct and low impedance. avoid form- ing ground loops. lvds outputs output traces and connections must be designed for 50 ? (100 ? differential) characteristic impedance. keep traces direct and minimize bends where possi- ble. avoid crossing ground and power plane breaks with signal traces. lvcmos outputs output traces and connections must be designed for 50 ? characteristic impedance. unused inputs standard logic inputs (resetn, csb, sclk, sdio, sdo) which will not be operated do not require connec- tion to ensure optimal adc performance. these in- puts can be left floating if they are not used. tri-level inputs (napslp, outmode, outfmt, clkdiv) accept a floating input as a valid state, and therefore should be biased according to th e desired functionality. definitions analog input bandwidth is the analog input fre- quency at which the spectral output power at the fundamental frequency (as determined by fft analy- sis) is reduced by 3db from its full-scale low-frequency value. this is also referred to as full power bandwidth. aperture delay or sampling delay is the time re- quired after the rise of the clock input for the sam- pling switch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. differential non-linearity (dnl) is the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternate method of specifying signal to noise-and-distortion ratio (sinad). in db, it is calculated as: enob = (sinad-1.76) / 6.02 gain error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage (less 2 lsb). it is typically expressed in percent. integral non-linearity (inl) is the deviation of each individual code from a line drawn from negative full- scale (1/2 lsb below the first code transition) through positive full-scale (1/2 lsb above the last code transi- tion). the deviation of any given code from this line is measured from the center of that code. least significant bit (lsb) is the bit that has the small- est value or weight in a digital word. its value in terms of input voltage is v fs /(2 n -1) where n is the resolution in bits. missing codes are output codes that are skipped and will never appear at the adc output. these codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. pipeline delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. power supply rejection ratio (psrr) is the ratio of a change in input voltage necessary to correct a change in output code that results from a change in power supply voltage. signal to noise-and-distortion (sinad) is the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below one half the clock frequency, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) is the ratio of the rms signal amplitude to the sum of all other spectral components below one-half the sampling frequency, excluding harmonics and dc. snr and sinad are either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the converter?s full-scale input power is used as the reference.
KAD5512HP rev 0.5 preliminary page 29 outline dimensions?72qfn spurious-free-dynamic range (sfdr) is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spuri- ous spectral component may or may not be a har- monic. two-tone sfdr is the ratio of the rms value of the lowest power input tone to the rms value of the peak spurious component, which may or may not be an imd product. figure 54. 72qfn dimensions
KAD5512HP rev 0.5 preliminary page 30 outline dimensions?48qfn figure 55. 48qfn dimensions
KAD5512HP rev 0.5 preliminary page 31 ordering guide the KAD5512HP is compliant with eu directive 2002/ 95/ec regarding the restri ction of hazardous sub- stances (rohs). contact kenet for a materials declaration for this product. revision history 21-feb-08: rev 0.5 initial version preliminary datasheet this datasheet contains preliminary technical data, which is subject to change without notice. contact kenet prior to initiating design activity using this product. model speed package temp. range KAD5512HP-25q72 250msps 72-qfn -40c to +85c KAD5512HP-21q72 210msps 72-qfn -40c to +85c KAD5512HP-17q72 170msps 72-qfn -40c to +85c KAD5512HP-25q48 250msps 48-qfn -40c to +85c KAD5512HP-21q48 210msps 48-qfn -40c to +85c KAD5512HP-17q48 170msps 48-qfn -40c to +85c KAD5512HP-12q72 125msps 72-qfn -40c to +85c KAD5512HP-12q48 125msps 48-qfn -40c to +85c

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